Semiconductor memories, such as random access memories (“RAMs”) and read only memories (“ROMs”), may include a keeper circuit coupled to a bit line to reduce leakage current and to reduce noise from corrupting data being read out of a memory bit cell coupled to the bit line. However, these conventional keeper circuits may still suffer from having high DC leakage currents, especially during low voltage operation, and result in the semiconductor memory having a slow operating time. Also, such conventional keepers are designed for worst-case coding, which can limit VCCmin operation and further increase power consumption.